The present invention relates in general to data processing systems and, in particular, to coherence protocols in multi-processor data processing systems.
A conventional multiprocessor (MP) computer system, such as a server computer system, includes multiple processing cores all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of directly addressable memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing core is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.
Because multiple processor cores may request write access to a same cache line of data and because modified cache lines are not immediately synchronized with system memory, an MP computer system typically implements a coherence protocol to ensure at least a minimum level of coherence among the various processor core's “views” of the contents of system memory. In particular, memory coherence requires, at a minimum, that after a processing unit accesses a copy of a memory block and subsequently accesses an updated copy of the memory block, the processing unit cannot again access the old copy of the memory block.
A coherence protocol typically defines a set of cache states stored in association with the cache lines held at each level of the cache hierarchy, as well as a set of coherence messages utilized to communicate the cache state information between cache hierarchies. In a typical implementation, the cache state information takes the form of the well-known MESI (Modified, Exclusive, Shared, Invalid) protocol or a variant thereof, and the coherency messages indicate a protocol-defined coherence state transition in the cache hierarchy of the requestor and/or the recipients of a memory access request.
The state to which each memory granule (e.g., cache line or sector) is set is dependent upon both a previous state of the data within the cache line and the type of memory access request received from a coherence participant. Accordingly, maintaining memory coherency in the system requires that the coherence participants communicate messages via the system interconnect indicating their intentions to read or write various memory locations. For example, when a processor core desires to write data to a target memory block, the processor core may first inform all coherence participants of its intention to write data to the target memory block and receive permission from all other coherence participants to carry out the write operation. The permission messages indicate that all other cached copies of the contents of the target memory block have been invalidated, thereby guaranteeing that other processor cores will not access a stale locally cached copy of the target memory block.